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8 Mbit LPC Flash
A Microchip Technology Company
CE#
LCLK
LFRAME#
SST49LF080A
Data Sheet
1st Start
Memory
Write
Cycle
Address1
Data
TAR
Sync
Start next
Command
LAD[3:0]
0000b
011Xb
A[31:28] A[27:24] A[23:20] A[19:16]
0101b
0101b
0101b
0101b
1010b
1010b
1111b
Tri-State 0000b
TAR
1 Clock 1 Clock
Load Address YYYY 5555H in 8 Clocks
Load Data AAH in 2 Clocks 2 Clocks
1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
CE#
LCLK
LFRAME#
2nd Start
Memory
Write
Cycle
Address1
Data
TAR
Sync
Start next
Command
LAD[3:0]
0000b
011Xb
A[31:28] A[27:24] A[23:20] A[19:16]
0010b
1010b
1010b
1010b
0101b
0101b
1111b
Tri-State 0000b
TAR
1 Clock 1 Clock
Load Address YYYY 2AAAH in 8 Clocks
Load Data 55H in 2 Clocks 2 Clocks
1 Clock
1 Clock
Write the 2nd command to the device in LPC mode.
CE#
LCLK
LFRAME#
3rd Start
Address1
Data
TAR
Sync
Start next
Command
LAD[3:0]
0000b
011Xb
A[31:28] A[27:24] A[23:20] A[19:16]
0101b
0101b
0101b
0101b
0000b
1010b
1111b
Tri-State 0000b
TAR
1 Clock 1 Clock
Load Address YYYY 5555H in 8 Clocks
Load Data A0H in 2 Clocks 2 Clocks
1 Clock
1 Clock
Write the 3rd command to the device in LPC mode.
CE#
LCLK
LFRAME#
Internal
4th Start
Memory
Write
Cycle
Address1
Data
TAR
Sync
program start
LAD[3:0]
0000b 011Xb
1 Clock 1 Clock
A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8]
Load Ain in 8 Clocks
A[7:4]
A[3:0]
D[3:0] D[7:4]
Load Data in 2 Clocks
1111b Tri-State 0000b
2 Clocks 1 Clock
TAR
Internal
program start
Write the 4th command (target locations to be programmed) to the device in LPC mode.
Note: 1. Address must be within memory address range specified in Table 4.
Figure 7: Program Command Sequence (LPC Mode)
1235 F06.0
?2011 Silicon Storage Technology, Inc.
21
DS25086A
11/11
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